SWS HQ CAIRO, EGYPT
- Responsible for RTL TO GDS implementation of multi-hierarchy designs.
- Chip level floorplan and integration planning and execution.
- Creation and management of partitions for soft macros including development of SDC.
- Work on design closure including timing, power, noise, and physical verification.
- Work closely with RTL design team to understand the design architecture and drive design physical planning aspects.
Experience / Requirements
- BS or MS in Electronic Engineering, Computer Engineering.
- 0-3 years of ASIC design, verification, and implementation.
- Expert in modern EDA tools for synthesis, test insertion, static timing analysis, place-and-route, clock tree synthesis, logic equivalence checking, DRC, LVS, DFM, parasitic extraction flows and low power design in advanced nodes.
- Comfortable working in a Linux environment and using version control (e.g., SVN).
- Familiar with Python, Perl, TCL, make, and other common scripting languages.
- Must be organized and self-motivated, able to turn abstract ideas into concrete designs.
- Must be a team player who enjoys working in a highly collaborative environment.
Potential candidates are welcome to forward their resumes with an email subject [PDE – Digital] to firstname.lastname@example.org