SWS HQ CAIRO, EGYPT
- Translating schematic-level analog and RF circuits into layout views using Cadence and Mentor tools in a timely fashion.
- Performing post-layout verification (DRC, LVS, etc) and parasitic extractions and debugging such issues.
- Interacting with design team to establish layout requirements and constraints.
Experience / Requirements
- B.Sc. in Electrical Engineering (0-2 years of experience), with an aptitude to learn and make a career in the area of VLSI layout design.
- Familiar in floor-planning, placement, layout, layout verification and parasitic extraction.
- Familiar with EDA tools such as Cadence and/or Mentor Graphics.
- Literate in CMOS fabrication process.
- Scripts writing experience is a plus.
- Digital back end and APR knowledge is a plus.
- Must be self-motivated and detail-oriented.
- Excellent communication skills.
- Very Good in English Language.
Potential candidates are welcome to forward their resumes with an email subject [PDE] to firstname.lastname@example.org